In accordance with progress of semiconductor technology, an electronic circuit board mounting a large number of LSIs (Large Scale Integrated circuit) on a printed wiring board (PWB) is widely used. Among such LSIs mounted on the PWB, the LSI having a large number of pins on it is also increasing.
In a design and development work of PWB, it needs to verify whether the design of wiring for the LSI mounted on the PWB are logically correct and whether wiring connections are correctly connected to proper points. In order to perform this kind of verification, it needs enormous amount of descriptive rules for defining each wiring connection on the PWB (hereinafter this rule is called as a connection rule). Therefore, big amount of man power is spent for producing the connection rule used in the verification work of each PWB, and long retrieval time among all connection rule for finding necessary connection rule which is suitably used in a respective proper verification work is necessary, and also many resources are needed for storing such enormous amount of connection rule in a verification apparatus.
The following patent documents disclose technologies relating to various verification works which are needed for efficiently performing design and development works of PWB on which plural LSIs are mounted.
Japanese Patent Application Laid-Open No. 1991-028971 discloses technology for a verification method of mask patterns which are required when mask layout data of LSI is created. According to this patent document, this technology can reduce verification processing time by performing verification of a plurality of cell data, which compose the mask layout data, at once in a cell level.
Japanese Patent Application Laid-Open No. 1994-120345 discloses technology relating to a layout verification work for an LSI design. According to this patent document, this technology can exclude a comparison mistake in comparison process of comparing between layout data and circuit data for a repeated structured cell part by using an electronic computer, and it can efficiently performs a design check work.
Japanese Patent Application Laid-Open No. 1997-167170 discloses technology relating to a design work of an electronic circuit having regular and repeated structures like a semiconductor memory and a liquid crystal display panel. According to this patent document, this technology can automatically perform a verification processing which is equivalent to the process in which the whole electronic circuit having regular and repeated structures is processed at once. This technology is characterized by setting regular and repeated structure model which can determine the regularity and individual data as structure definition information.
Japanese Patent Application Laid-Open No. 1997-237289 discloses technology for automatically generating the hardware description which is used for logic verification of an electronic circuit and is generated from a circuit diagram of the electronic circuit. According to this patent document, this technology can automatically generate the hardware description, which represents logic functions of the electronic circuit for the logic verification, from the circuit diagram without changing connection information on the circuit diagram. This technology is characterized in that deletion information for analog components, like resistors, which are shown in the circuit diagram and are not needed for the logic verification, is added, and the deletion information is effectively used for generating the hardware description automatically.
Japanese Patent Application Laid-Open No. 1998-254938 discloses technology for converting a large-scale digital analog mixed circuit into a suitable circuit to be used for high speed and efficient digital simulation. According to this patent document, this technology can efficiently perform model conversion according to conversion rules for the digital analog mixed circuit, and a converted circuit in accordance with the characteristics of the logic simulator to be used is obtained.